基本命令セット RV32I

ロード / ストア

• LW (I) ... add, op1, op2_imi

• SW (S) ... add op1, op2_ims

加算

• ADD (R) ... add, op1, op2

• ADDI (I) ... add, op1, imi

減算

• SUB (R) ... sub op1, op2

論理演算

• AND (R) ... and, op1, op2

• OR (R) ... or, op1, op2

• XOR (R) ... xor, op1, op2

• ANDI (I) ... and, op1, op2_imi

• ORI (I) ... or, op1, op2_imi

• XORI (I) ... xor, op1, op2_imi

シフト

• SLL (R) ... sll, op1, op2 ... (op1 << op2(4, 0))(31, 0)

• SRL (R) ... srl, op1, op2 ... (op1 >> op2(4, 0)).asUInt()

• SRA (R) ... sra, op1, op2 ... (op1.asSInt() >> op2(4, 0)).asUInt()

• SLLI (I) ... sll, op1, op2_imi

• SRLI (I) ... srl, op1, op2_imi

• SRAI (I) ... sra, op1, op2_imi

比較

• SLT (R) ... slt, op1, op2 ... (op1.asSInt() < op2.asSInt()).asUInt()

• SLTU (R) ... sltu, op1, op2 ... (op1 < op2).asUInt()

• SLTI (I) ... slt, op1, op2_imi

• SLTIU (I) ... sltu, op1, op2_imi

条件分岐

• BEQ (I) ... beq, op1, op2 ... (op1 === op2)

• BNE (I) ... bne, op1, op2 ... !(op1 === op2)

• BLT (I) ... blt, op1, op2 ... (op1.asSInt() < op2.asSInt())

• BGE (I) ... bge, op1, op2 ... !(op1.asSInt() < op2.asSInt())

• BLTU (I) ... bltu, op1, op2 ... (op1 < op2)

• BGEU (I) ... bgeu, op1, op2 ... !(op1 < op2)

( br_target := pc + imb )

ジャンプ

• JAL (J) ... add, pc, op2_imj

• JALR (I) ... jalr, op1, op2_imi ... (op1 + op2) & !(1.U(32.W))

即値ロード

• LUI (U) ... add, 0, op2_imu

• AUIPC (U) ... add, pc, op2_imu

CSR

• CSRRW (I) ... copy, op1, 0 ... csr_wdata = op1

• CSRRWI (I, z) ... copy, op1_imz, 0

• CSRRS (I) ... copy, op1, 0 ... csr_wdata = csr_rdata | op1

• CSRRSI (I, z) ... copy, op1_imz, 0

• CSRRC (I) ... copy, op1, 0 ... csr_wdata = csr_rdata & !op1

• CSRRCI (I, z) ... copy, op1_imz, 0

( csr_addr = inst(31, 20)) )

例外

• ECALL (I) ... 0, 0, 0 ... csr_wdata = 11.U(32.W)

( csr_addr = 0x342.U(3.W) )