テスト・シミュレーションのメモ（System verilog）
- `timescale
- `default_nettype
- module
- clk, rst
- その他信号
- その他定数
- テストするモジュールの宣言
- initial
- $display
- logic宣言した信号初期化
- クロック生成
- クロックごとの処理
- 遅延追加
- デバッグ出力
- $finish
だんだん完成に近づいていく．
`timescale
`timescale 1ns / 100ps
`default_nettype
`timescale 1ns / 100ps `default_nettype none ... `default_nettype wire
module
`timescale 1ns / 100ps
`default_nettype none
module testcore();
...
endmodule
`default_nettype wire
clk, rst
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
endmodule
`default_nettype wire
その他信号
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
endmodule
`default_nettype wire
その他定数
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
endmodule
`default_nettype wire
テストするモジュールの宣言
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
endmodule
`default_nettype wire
initial
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
initial begin
...
end
endmodule
`default_nettype wire
$display
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
initial begin
$display("------------ start ---------------");
end
endmodule
`default_nettype wire
logic宣言した信号初期化
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
initial begin
$display("------------ start ---------------");
clk = 0;
foo = 0;
bar = 0;
end
endmodule
`default_nettype wire
クロック生成
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
initial begin
$display("------------ start ---------------");
clk = 0;
foo = 0;
bar = 0;
for (i=1; i<=maxclocks; i++) begin
for (j=0; j<2; j++) begin
clk = ~clk;
end
end
end
endmodule
`default_nettype wire
クロックごとの処理
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
initial begin
$display("------------ start ---------------");
clk = 0;
foo = 0;
bar = 0;
for (i=1; i<=maxclocks; i++) begin
if (i == 1000) begin
foo = 1;
end
if (i == 2000) begin
foo = 0;
end
if (i == 3000) begin
bar = 1;
end
if (i == 4000) begin
bar = 0;
end
for (j=0; j<2; j++) begin
clk = ~clk;
end
if (complete) begin
break;
end
end
end
endmodule
`default_nettype wire
遅延追加
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [31:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
initial begin
$display("------------ start ---------------");
clk = 0;
foo = 0;
bar = 0;
for (i=1; i<=maxclocks; i++) begin
if (i == 1000) begin
foo = 1;
end
if (i == 2000) begin
foo = 0;
end
if (i == 3000) begin
bar = 1;
end
if (i == 4000) begin
bar = 0;
end
for (j=0; j<2; j++) begin
#10
clk = ~clk;
end
if (complete) begin
break;
end
end
end
endmodule
`default_nettype wire
デバッグ出力
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [2:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
initial begin
$display("------------ start ---------------");
clk = 0;
foo = 0;
bar = 0;
for (i=1; i<=maxclocks; i++) begin
if (i == 1000) begin
foo = 1;
end
if (i == 2000) begin
foo = 0;
end
if (i == 3000) begin
bar = 1;
end
if (i == 4000) begin
bar = 0;
end
for (j=0; j<2; j++) begin
#10
clk = ~clk;
end
if (complete) begin
break;
end
end
$display("finish clk :%5d", i);
$display("tmp1 :%5d", tmp1);
$display("tmp2 :%5d, %5d, %5d", tmp2[0], tmp2[1], tmp2[2]);
end
endmodule
`default_nettype wire
$finish
`timescale 1ns / 100ps
`default_nettype none
module testcore();
logic clk;
wire rst = 1;
logic foo;
logic bar;
wire [31:0] tmp1;
wire [31:0] tmp2 [2:0];
wire complete;
int maxclocks = 10000000;
int i, j, k, l;
moduleA _moduleA(clk, rst, foo, bar, tmp1, tmp2, complete);
initial begin
$display("------------ start ---------------");
clk = 0;
foo = 0;
bar = 0;
for (i=1; i<=maxclocks; i++) begin
if (i == 1000) begin
foo = 1;
end
if (i == 2000) begin
foo = 0;
end
if (i == 3000) begin
bar = 1;
end
if (i == 4000) begin
bar = 0;
end
for (j=0; j<2; j++) begin
#10
clk = ~clk;
end
if (complete) begin
break;
end
end
$display("finish clk :%5d", i);
$display("tmp1 :%5d", tmp1);
$display("tmp2 :%5d, %5d, %5d", tmp2[0], tmp2[1], tmp2[2]);
$display("--------------finish---------------");
$finish;
end
endmodule
`default_nettype wire
